A sigma-delta analog-to-digital converter (“ΣΔ ADC”) is an electronic device that receives an analog input signal and generates a digital representation of the input signal. Conventional ADCs perform a similar function but require high oversampling of the analog input signal or increasing the number of bits (quantization levels) in order to minimize quantization noise—a by-product of the analog-to-digital conversion process.
Sigma-delta ADCs include an error correction loop that relaxes oversampling requirements for the analog-to-digital conversion process and shapes the frequency of the quantization noise to push it out of an area (frequency) of interest. The error correction loop may include a shuffler (sometimes referred to as a scrambler or a mismatch-shaper) and a feedback digital-to-analog converter (“DAC”). The shuffler may not be required if the loop is for a single bit. The shuffler receives an ADC output signal from an internal ADC (quantizer) and generates selection signals which control charge transfer for unit elements (resistors, capacitors, or current sources) of the DAC. The DAC unit elements may introduce mismatch noise into the frequency of interest, due to mismatch errors introduced into unit elements during manufacturing. Based on the selection, the DAC generates an output signal which is subtracted from the input signal. Thus, the noise transfer function of the error correction loop performs shaping of the quantization noise for the ΣΔ ADC output signal.
The function of a shuffler is known at an academic level, however, production implementations may vary. Shufflers might be implemented using multi-order (i.e., first order, second order, etc.) frequency shaping signal processing techniques to minimize unit element mismatch noise in the frequency of interest. Increased order results in increased minimization of mismatch noise in the frequency of interest. FIG. 1 illustrates a block diagram of a possible implementation of a second order shuffler 100.
As illustrated in FIG. 1, the second order shuffler 100 includes: a sorter 110, two stages of N accumulators 120.1-120.N, 130.1-130.N, N feed forward buffers 140.1-140.N, and N adders 150.1-150.N. The shuffler 100 receives an N-valued output signal y[n] from an ADC over times ‘n’. The shuffler 100 generates N selection signals ySk[n], which engage unit elements within a DAC to generate an electrical charge, current or voltage in a feedback path of a ΣΔ ADC.
The sorter 110 ranks an accumulated history of unit element selection signals, labeled “dk[n],” and maps the output signal y[n] to selection signals ySk[n] based on the ranking. Operation of the sorter 110 can be described mathematically as an error signal ek[n] (not shown) added to the accumulated history of selection signals dk[n] to generate the selection signals ySk[n]. The error signal ek[n] can be seen as the difference between the accumulated history of selection signals dk[n] and the selection signals ySk[n].
Each first stage accumulator 120.1-120.N performs accumulation for values of respective selection signals ySk[n]. An output from each first stage accumulator 120.1-120.N is labeled “w1k[n]”. Similarly, each second stage accumulator 130.1-130.N generates an output accumulation, labeled “w2k[n].” The feed forward buffers 140.1-140.N scale the outputs of the first stage accumulators 120.1-120.N for combination with the outputs of the second stage accumulators 130.1-130.N. A scaling factor ‘X’ determines the weighting for the first stage accumulator 120.1-120.N outputs w1k[n]. The shuffler 100 may include buffers 160.1-160.N to provide a negative value of the selection signals ySk[n] to the first stage accumulator 120.1-120.N. In addition to the feed forward topology introduced in FIG. 1, the error feed-back topologies and signal feed-back topologies can be used to implement the transfer function of the circuit.
For a processing loop within the shuffler 100 where X=2, the various signals are represented by a system of equations as follows:w1k[n]=w1k[n−1]−ySk[n−1]w2k[n]=w2k[n−1]+w1k[n−1]dK[n]=w2k[n]+2w1k[n]ySk[n]=dk[n]+eK[n]  Eqn. 1
The relationship between the ΣΔ ADC output signal y[n], which has a value between 0−N, and the N selection signals ySk[n], which have values of +1 or −1 (or in alternative embodiment values −1, 0 or +1), is represented by the following equation:
                                          ∑                          k              =              1                        N                    ⁢                                    y                              S                k                                      ⁡                          [              n              ]                                      =                              2            ⁢                          y              ⁡                              [                n                ]                                              -          N                                    Eqn        .                                  ⁢        2            
A Z transform of the selection signal, which illustrates the second order shaping of the error signal is expressed as:YSk(z)=(1−z−1)2·Ek(z)   Eqn. 3The second order shuffler 100, however, may become unstable when signals input to the accumulator stages 120.1-120.N, 130.1-130.N are not zero-mean, which is the case for shufflers used in ΣΔ ADCs. When the input signals are not zero mean, the accumulators 120.1-120.N, 130.1-130.N might accumulate in an unbounded manner and need to be saturated at upper and lower bounds. The saturation, in effect, limits the frequency shaping function of the shuffler 100 to first-order frequency shaping. First order frequency shaping can degrade SNR for the ΣΔ ADC output signal y[t].
Accordingly, a need in the art exists for a stable second order shuffler for a ΣΔ ADC.